The present invention relates to a structure for measuring mask and layer alignment in semiconductor fabrication processes.
Modern integrated circuits (ICs) are fabricated in multiple layers on a silicon wafer, each layer representing a 2-dimensional layout of device elements (e.g., gates, gate dielectrics, source/drain regions, etc.). Typically, photolithographic techniques are used to produce the patterns for each layer, with those patterns controlling the subsequent formation of the device elements in a particular layer. To ensure proper function of an IC, the multiple layers making up that IC must be precisely aligned, meaning that the associated masks used in the photolithographic process steps must be aligned. It is therefore important to be able to monitor and measure this mask or layer alignment.
A common method for mask alignment involves target markings on the masks and wafers. Through the use of high-magnification equipment or similar optical sensing techniques, misalignment can be visually measured and monitored. However, this manual technique is time-consuming and susceptible to human error. Consequently, such a technique is not feasible for gathering a large statistical base of information or monitoring a relatively large number of wafers.
To overcome the aforementioned limitations of manual measurement techniques, electrical test methods have been developed. Conventional electrical alignment test methods involve the creation of special multi-layer conductive elements using the same fabrication processes being used to produce the actual ICs. The multi-layer conductive elements are configured such that any misalignment between layers results in a change in the resistance of the conductive elements. By comparing the measured resistance with a baseline (i.e., no misalignment) resistance value, the total amount of misalignment between layers can be determined.
FIG. 1 shows an example of a conventional electrical alignment test structure 100, as described in U.S. Pat. No. 4,571,538, issued Feb. 18, 1986 to Chow. Test structure 100 comprises a plurality of u-shaped features 130, a plurality of rectangular features 120, a plurality of square features 110, and contact pads A, B, and C. The plurality of u-shaped features 130 are formed in a polysilicon layer. The pattern of square features 110 is formed in a contact layer. Finally, the pattern of rectangular features 120 and pads A, B, and C are formed in a metal layer.
To form test structure 100, the plurality of u-shaped features 130 are formed in the polysilicon layer during the same process steps used to form other polysilicon layer features in the IC. Next, the plurality of square features 110 are formed during a contact process step, and the plurality of rectangular features 120, and pads A, B, and C are formed during a metallization process step. A dielectric layer (not shown) isolates the plurality of u-shaped features 130 from the plurality of rectangular features 120. Therefore, the plurality of square features 110 provide the only electrical contact between the u-shaped features 130 and the rectangular features 120.
Test structure 100 enables measurement of any misalignment between the polysilicon layer (features 130) and the contact layer (features 110) in the Y-direction (as indicated by the axes in FIG. 1). If the contact layer and polysilicon layers are perfectly aligned, the electrical paths between pads A and C and pads B and C are substantially the same length, and therefore the resistances between pads A and C (Rac) and between pads B and C (Rbc) are substantially the same. However, if the contact layer is shifted in the positive Y-direction (upwards) with respect to the polysilicon layer, the electrical path between pads A and C becomes longer than the path between pads B and C, and therefore resistance Rac becomes greater than resistance Rbc. Likewise, if the contact layer is shifted in the negative Y-direction (downwards) with respect to the polysilicon layer, resistance Rac becomes less than resistance Rbc. In this manner, the Y-direction alignment of the polysilicon and contact layers (and masks) can be measured. A second test structure can be oriented perpendicular to test structure 100 to provide X-axis alignment measurement.
FIG. 2 shows another example of a conventional alignment test structure 200, as described in U.S. Pat. No. 4,386,459, issued Jun. 7, 1983 to Boulin. Test structure 200 comprises a serpentine conductive member 210, contact pads A-I, and contacts Ca-Ci. Conductive member 210 comprises contiguous linear elements 211-220 forming two interconnected S-shaped elements in a first layer, such as a metal, polysilicon, or diffusion layer. The first S-shaped element comprises horizontal elements 211, 213, and 215, and vertical elements 212 and 214. The second S-shaped element comprises vertical elements 216, 218, and 220, and horizontal elements 217 and 219. Contact pads A-I are formed in a second layer, such as a metal layer, that overlies an insulating layer (not shown) on the first layer. Contacts Ca-Ci are formed in a third layer between the first and second layers, providing electrical contact between contact pads A-I and conductive member 210.
Contact pads A-I are located along conductive member 210 such that when the first and second layers are properly aligned, the electrical path from pad B to pad C (Pbc) is the same length as the electrical path from pad C to pad D (Pcd), and the electrical path from pad F to pad G (Pfg) is the same length as the electrical path from pad G to pad H (Pgh). Under such circumstances, the resistances between pads B and C (Rbc) and pads C and D (Rcd) would be the same, as would the resistances between pads F and G (Rfg) and pads G and H (Rgh). Misalignment between the first and second layers would change the relative lengths of the electrical paths described above, thereby creating resistance differentials indicative of the misalignment. For example, if the second mask (contact pads A-I) is shifted in the positive Y-direction with respect to the first mask (conductive element 210), the length of electrical path Pfg is reduced, while the length of electrical path Pgh is increased. Consequently, resistance Rfg becomes smaller than resistance Rgh, and a positive Y-axis misalignment is indicated. Similarly, if the second mask is shifted in the positive X-direction with respect to the first mask, the lengths of electrical paths Pbc and Pcd are decreased and increased, respectively. Therefore, resistance Rbc becomes smaller than resistance Rcd, thereby indicating a positive X-axis misalignment.
FIG. 3a shows another example of a conventional alignment test structure 300, as described in U.S. Pat. No. 5,770,995, issued Jun. 23, 1998 to Kamiya. Test structure 300 comprises two conductive regions 310 in a first layer, four triangular openings 320 in a second layer formed over the first layer, and contact pads A and B and an interconnect 330 in a third layer formed over the second layer. The four triangular openings 320 are arranged linearly, with two triangular openings 320 being formed over one of the conductive regions 310, and the other two triangular openings 320 being formed over the other conductive region 310. Contact pad A extends over one of the outer triangular openings 320, while contact pad B extends over the other outer triangular opening 320, with interconnect 330 being formed over the two inner triangular openings 320.
As shown in cross-section Sxe2x80x94S of FIG. 3b, contact pads A and B and interconnect 330 (third layer) are insulated from conductive regions 310 (first layer) by a dielectric layer 350 (second layer). However, electrical contact is made between the first and third layers where contact pads A and B and interconnect 330 extend through triangular openings 320 to meet conductive regions 310. A contact layer can be included under pads A and B and interconnect 330 to improve the electrical contact between the first and third layers.
Referring back to FIG. 3a, because all triangular openings 320 are oriented in the same direction, the contact area between pads A and B and interconnect 330 and conductive regions 310 varies with the relative positions of the first and third layers in the Y-direction (vertically). The resulting change in resistance between pads A and B can then be measured to detect misalignment between the first and third layers. For example, if the third layer is shifted in the positive Y-direction (upward) with respect to the first layer, the contact areas between contact pads A and B and interconnect 330 and conductive regions 310 are reduced, thereby increasing the resistance between pads A and B. Similarly, if the third layer is shifted in the negative Y-direction (downward) with respect to the first layer, the resistance between pads A and B is reduced due to the increased electrical contact area. A second test structure can be perpendicularly oriented with respect to test structure 300 to provide X-direction (horizontal) misalignment detection.
While the aforementioned electrical alignment test structures can be used to detect misalignment between electrically connected layers, modern ICs typically also require fine alignment between layers that do not make direct electrical contact. For example, the gate of a metal-oxide-semiconductor (MOS) transistor must be aligned with the diffusion region of the transistor, even though the two are separated by a dielectric layer. Accordingly, it is desirable to provide an electrical alignment test structure that enables measurement of alignment between layers that do not make direct electrical contact. It is also desirable to provide a simplified alignment test structure that does not require complex layout paths (FIGS. 1 and 2) or irregular angles (FIG. 3a), thereby substantially decreasing design complexity and manufacturing cost.
The present invention provides an electrical alignment test structure for monitoring and measuring misalignment between layers (or associated masks) of an IC.
A polysilicon-diffusion test structure in accordance with an embodiment of the present invention comprises a target region, two contact pads coupled to the target region, and an alignment feature. The target region, contact pads, and alignment feature are in different layers of the IC, wherein the alignment feature is electrically isolated from the target region. According to an aspect of the present invention, the target region is formed in the diffusion layer of the IC and the alignment feature is formed in the polysilicon layer of the IC. The alignment feature is positioned over the target region and serves as a partial mask during doping of the target region. The position of the alignment feature with respect to the target region defines the size of a conductive channel in the target region for carrying current between the two contact pads. The measured pad to pad resistance can be compared to a baseline (no misalignment) resistance value to check for misalignment between the electrically isolated polysilicon and diffusion layers of the IC.
Multiple polysilicon-diffusion test structures can be combined in an array in accordance with an embodiment of the present invention. By properly configuring the test structures in two mirror-image sets, the array can measure the amount of misalignment between the polysilicon and diffusion layers. If each set is configured such that the nominal conductive channel width of each test structure is increased by a fixed amount over the previous test structure when moving away from the centerline, then characteristic current curves can be graphed for each set. If the polysilicon and diffusion layers are aligned, the characteristic curves of the two sets are the same. However, if the two layers are misaligned, one characteristic curve is shifted to the right, and the other to the left. The amount of misalignment can be determined by measuring the amount of shift for either curve or halving the distance between both shifted characteristic curves.
A well-diffusion test structure in accordance with another embodiment of the present invention comprises a target region, two contact pads coupled to the target region, and an alignment feature. The target region, contact pads, and alignment feature are in different layers of the IC. According to an aspect of the present invention, the target region is formed in the well layer of the IC and the alignment feature is formed in the diffusion layer of the IC. The alignment feature is formed over a portion of the target region, and a much thicker field oxide is formed over the rest of the test structure. The portions of the field oxide over the target region consume much more of the silicon substrate than the thin gate oxide (alignment structure), thereby reducing the conduction area of the target region. Therefore, the position of the alignment structure with respect to the target region defines the size of the conductive channel between the contact pads. The measured pad to pad resistance of the test structure can be compared to a baseline (no misalignment) resistance value to check for misalignment between the well and diffusion layers of the IC.
Multiple well-diffusion test structures can be combined in an array in accordance with another embodiment of the present invention. By properly configuring the test structures in two mirror image sets, the array can measure the amount of misalignment between the well and diffusion layers. If each set is configured such that the nominal conductive channel cross sectional area is decreased by a fixed increment over the previous test structure when moving away from the centerline, then characteristic resistance curves can be graphed for each set. If the well and diffusion layers are aligned, the characteristic curves of the two sets are the same. However, if the two layers are misaligned, one characteristic curve is shifted to the right, and the other to the left. The amount of misalignment can be determined by measuring the amount of shift for either curve or halving the distance between both shifted characteristic curves.
Another polysilicon-diffusion test structure in accordance with another embodiment of the present invention comprises a target region and an alignment feature. According to an aspect of the present invention, the target region is formed in the diffusion layer of the IC and the alignment feature is formed in the polysilicon layer of the IC. The alignment feature is formed over a central portion of the target region, after which the target region is doped. The alignment feature serves as a mask for the target region during doping, thereby forming the source and drain regions in the diffusion layer. The relative positions of the polysilicon and diffusion layers therefore determine the relative sizes of the source and drain regions of the test structure. The measured current flow of the test structure can be compared to a baseline (no misalignment) current value to check for misalignment between the electrically isolated polysilicon and diffusion layers of the IC. The sensitivity of the test structure current flow to misalignment can be enhanced by modifying the outlines of the drain and source regions.
Multiple polysilicon-diffusion test structures can be combined in an array in accordance with another embodiment of the present invention. By properly configuring the test structures in two mirror image sets, the array can measure the amount of misalignment between the polysilicon and diffusion layers. If each set is configured such that the nominal distance between the alignment feature and an edge of the drain region is increased by a fixed increment over the previous test structure when moving away from the centerline, then characteristic current curves can be graphed for each set. If the polysilicon and diffusion layers are aligned, the characteristic curves of the two sets are the same. However, if the two layers are misaligned, one characteristic curve is shifted to the right, and the other to the left. The amount of misalignment can be determined by measuring the amount of shift for either curve or halving the distance between both shifted characteristic curves.
A well-diffusion test structure in accordance with another embodiment of the present invention comprises a target region and an alignment region. The target region is formed in a well layer of an IC, while the alignment region is formed in a diffusion layer of the IC. The alignment region is formed within the target region, and is doped using the opposite dopant type from the target region. The alignment region and target region form a diode at their PN junction. When the diode is reverse biased, only a small leakage current flows through the alignment region. However, if the alignment region is close to the edge of the target region, the depletion layer under the alignment region can interact with the substrate outside the target region. Additional current can then flow directly from the alignment region to the substrate. The closer the alignment region is formed to the edge of the target region, the larger the total current flow through the alignment region.
The relative positions of the diffusion and well layers therefore define the amount of current flow through the test structure. A measured current can then be compared to a baseline (no misalignment) current value to check for misalignment between the well and diffusion layers of the IC. The test structure includes only basic shapes and therefore provides a simple means for measuring misalignment.
Multiple well-diffusion test structures can be combined in an array in accordance with another embodiment of the present invention. By properly configuring the test structures in two mirror image sets, the array can measure the amount of misalignment between the well and diffusion layers. If each set is configured such that the nominal distance between the alignment region and an edge of the target region is increased by a fixed increment over the previous test structure when moving away from the centerline, then characteristic leakage current curves can be graphed for each set. If the well and diffusion layers are aligned, the characteristic curves of the two sets are the same. However, if the two layers are misaligned, one characteristic curve is shifted to the right, and the other to the left. The amount of misalignment can be determined by measuring the amount of shift for either curve or halving the distance between both shifted characteristic curves.
The present invention will be more fully understood in view of the following description and drawings.